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d a t a sh eet product speci?cation supersedes data of september 1993 file under integrated circuits, ic06 1998 jun 10 integrated circuits 74hc/hct181 4-bit arithmetic logic unit for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
1998 jun 10 2 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 features full carry look-ahead for high-speed arithmetic operation on long words provides 16 arithmetic operations: add, subtract, compare, double, plus 12 others provides all 16 logic operations of two variables: exclusive-or, compare, and, nand, nor, or plus 10 other logic operations output capability: standard, a=b open drain i cc category: msi general description the 74hc/hct181 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct181 are 4-bit high-speed parallel arithmetic logic units (alu). controlled by the four function select inputs (s 0 to s 3 ) and the mode control input (m), they can perform all the 16 possible logic operations or 16 different arithmetic operations on active high or active low operands (see function table). when the mode control input (m) is high, all internal carries are inhibited and the device3 performs logic operations on the individual bits as listed. when m is low, the carries are enabled and the 181 performs arithmetic operations on the two 4-bit words. the 181 incorporates full internal carry look-ahead and provides for either ripple carry between devices using the c n+4 output, or for carry look-ahead between packages using the carry propagation ( p) and carry generate ( g) signals. p and g are not affected by carry in. when speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the carry output (c n+4 ) signal to the carry input (c n ) of the next unit. for high-speed operation the device is used in conjunction with the 182 carry look-ahead circuit. one carry look-ahead package is required for each group of four 181 devices. carry look-ahead can be provided at various levels and offers high-speed capability over extremely long word lengths. the comparator output (a=b) of the device goes high when all four function outputs ( f 0 to f 3 ) are high and can be used to indicate logic equivalence over 4 bits when the unit is in the subtract mode. a=b is an open collector output and can be wired-and with other a=b outputs to give a comparison for more than 4 bits. the open drain output a=b should be used with an external pull-up resistor in order to establish a logic high level. the a=b signal can also be used with the c n+4 signal to indicate a > b and a < b. the function table lists the arithmetic operations that are performed without a carry in. an incoming carry adds a one to each operation. thus, select code lhhl generates a minus b minus 1 (2s complement notation) without a carry in and generates a minus b when a carry is applied. because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus, a carry is generated when there is no under-flow and no carry is generated when there is underflow. as indicated, the 181 can be used with either active low inputs producing active low outputs or with active high inputs producing active high outputs. for either case the table lists the operations that are performed to the operands. ordering information type number package name description version 74hc181n3; 74hct181n3 dip24 plastic dual in-line package; 24 leads (300 mil) sot222-1 74hc181n; 74hct181n dip24 plastic dual in-line package; 24 leads (600 mil) sot101-1 74HC181D; 74hct181d so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1998 jun 10 3 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 quick reference data gnd = 0 v; t amb =25 c; t r =t f =6ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v symbol parameter conditions typical unit hc hct t phl / t plh propagation delay c l = 15 pf; v cc =5v a n or b n to a=b 28 30 ns c n to c n+ 41721ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per l package notes 1 and 2 90 92 pf fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol. a b
1998 jun 10 4 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 pin description pin no. symbol name and function 1, 22, 20, 18 b 0 to b 3 operand inputs (active low) 2, 23, 21, 19 a 0 to a 3 operand inputs (active low) 6, 5, 4, 3 s 0 to s 3 select inputs 7c n carry input 8 m mode control input 9, 10, 11, 13 f 0 to f 3 function outputs (active low) 12 gnd ground (0 v) 14 a=b comparator output 15 p carry propagate output (active low) 16 c n+4 carry output 17 g carry generate output (active low) 24 v cc positive supply voltage fig.4 functional diagram. o k, halfpage mbk219 a 0 a 1 a 2 2 23 21 19 1 22 20 18 15 17 14 16 13 11 10 9 a 3 b 0 b 1 c n + 4 f 3 f 2 f 1 f 0 a=b g b 2 p b 3 7 c n 6 s 0 5 s 1 4 s 2 3 s 3 8m fig.5 active high operands - active low operands.
1998 jun 10 5 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 function tables notes to the function tables 1. each bit is shifted to the next more significant position. 2. arithmetic operations expressed in 2s complement notation. h = high voltage level l = low voltage level mode select inputs active high inputs and outputs s 3 s 2 s 1 s 0 logic (m=h) arithmetic (2) (m=l; c n =h) l l l l l l l l l l h h l h l h a a + b ab logical 0 a a+b a+ b minus 1 l l l l h h h h l l h h l h l h ab b a ? b a b a plus a b (a + b) plus a b a minus b minus 1 a b minus 1 h h h h l l l l l l h h l h l h a+b a ? b b ab a plus ab a plus b (a + b) plus ab ab minus 1 h h h h h h h h l l h h l h l h logical 1 a+ b a+b a a plus a (1) (a + b) plus a (a + b) plus a a minus 1 notes to the function tables 1. each bit is shifted to the next more significant position. 2. arithmetic operations expressed in 2s complement notation. h = high voltage level l = low voltage level mode select inputs active low inputs and outputs s 3 s 2 s 1 s 0 logic (m=h) arithmetic (2) (m=l; c n =l) l l l l l l l l l l h h l h l h a ab a+b logical 1 a minus 1 ab minus 1 a b minus 1 minus 1 l l l l h h h h l l h h l h l h a + b b a ? b a+ b a plus (a + b) ab plus (a + b) a minus b minus 1 a+ b h h h h l l l l l l h h l h l h ab a ? b b a + b a plus (a + b) a plus b a b plus (a + b) a+b h h h h h h h h l l h h l h l h logical 0 a b ab a a plus a (1) ab plus a a b plus a a
1998 jun 10 6 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 fig.6 logic diagram.
1998 jun 10 7 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 table 1 sum mode test function inputs s 0 =s 3 = 4.5 v, m = s 1 =s 2 =0v table 2 differential mode test function inputs s 1 =s 2 = 4.5 v, m = s 0 =s 3 =0v table 3 logic mode test function inputs m = s 1 =s 2 = 4.5 v, s 0 =s 3 =0v parameter input under test other input, same bit other data inputs output under test apply 4.5 v apply gnd apply 4.5 v apply gnd t plh / t phl a i b i none remaining a and bc n f i t plh / t phl b i a i none remaining a and bc n f i t plh / t phl a i b i none none remaining a and b, c n p t plh / t phl b i a i none none remaining a and b, c n p t plh / t phl a i none b i remaining b remaining a, c n g t plh / t phl b i none a i remaining b remaining a, c n g t plh / t phl a i none b i remaining b remaining a, c n c n+4 t plh / t phl b i none a i remaining b remaining a, c n c n+4 t plh / t phl c n none none all a all b any f or c n+4 parameter input under test other input, same bit other data inputs output under test apply 4.5 v apply gnd apply 4.5 v apply gnd t plh / t phl a i none b i remaining a remaining b, c n f i t plh / t phl b i a i none remaining a remaining b, c n f i t plh / t phl a i none b i none remaining a and b, c n p t plh / t phl b i a i none none remaining a and b, c n p t plh / t phl a i b i none none remaining a and b, c n g t plh / t phl b i none a i none remaining a and b, c n g t plz / t pzl a i none b i remaining a remaining b, c n a=b t plz / t pzl b i a i none remaining a remaining b, c n a=b t plh / t phl a i b i none none remaining a and b, c n c n+4 t plh / t phl b i none a i none remaining a and b, c n c n+4 t plh / t phl c n none none all a and b none any f or c n+4 parameter input under test other input, same bit other data inputs output under test apply 4.5 v apply gnd apply 4.5 v apply gnd t plh / t phl a i b i none none remaining a and b, c n f i t plh / t phl b i a i none none remaining a and b, c n f i
1998 jun 10 8 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 ratings (for a=b output only) limiting values in accordance with the absolute maximum system (iec 134) voltage are referenced to gnd (ground = 0 v) dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi voltages are referenced to gnd (ground = 0 v) note to the dc characteristics 1. the maximum operating output voltage (v o(max) ) is 6.0 v. symbol parameter min. max. unit conditions v o dc output voltage - 0.5 +7.0 v - i ok dc output diode current 20 ma for v o <- 0.5 v - i o dc output source or sink current 25 ma for - 0.5 v < v o symbol parameter t amb ( c) unit test conditions 74hc v cc (v) v il other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. i oz high level output leakage current 0.5 5.0 10.0 m a 2.0 to 6.0 v il note 1 v o =0or6v
1998 jun 10 9 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) mode other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay c n to c n+4 55 20 16 165 33 28 205 41 35 250 50 43 ns 2.0 4.5 6.0 sum diff m=0v; fig.9; tables 1 and 2 t phl / t plh propagation delay c n to f n 69 25 20 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 sum diff m=0v; fig.9; tables 1 and 2 t phl / t plh propagation delay a n to g 72 26 21 210 42 36 265 53 45 315 63 54 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b n to g 77 28 22 230 46 39 290 58 49 345 69 59 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay a n to g 76 26 21 215 43 37 270 54 46 320 65 55 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b n to g 77 28 22 240 48 41 300 60 51 360 72 61 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay a n to p 61 22 18 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b n to p 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay a n to p 55 20 16 170 34 29 215 43 37 255 51 43 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b n to p 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay a i to f i 77 28 22 230 46 39 290 58 49 345 69 59 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b i to f i 85 31 25 255 51 43 320 64 54 385 77 65 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay a i to f i 77 28 22 235 47 40 295 59 50 355 71 60 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b i to f i 83 31 24 255 51 43 320 64 54 385 77 65 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2
1998 jun 10 10 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 note to the ac characteristics 1. for the open drain output (a=b) only t thl is valid. t phl / t plh propagation delay a i to f i 74 27 22 230 46 39 290 58 49 345 69 59 ns 2.0 4.5 6.0 logic m = 4.5 v; fig.8; table 3 t phl / t plh propagation delay b i to f i 83 30 24 255 51 43 320 64 54 385 77 65 ns 2.0 4.5 6.0 logic m = 4.5 v; fig.8; table 3 t phl / t plh propagation delay a n to c n+4 80 29 23 235 47 40 295 59 50 355 71 60 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.8; table 1 t phl / t plh propagation delay b n to c n+4 80 29 23 235 47 40 295 59 50 355 71 60 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.8; table 1 t phl / t plh propagation delay a n to c n+4 77 28 22 235 47 40 295 59 50 355 71 60 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.10; table 2 t phl / t plh propagation delay b n to c n+4 85 31 25 255 51 43 320 64 54 385 77 65 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.10; table 2 t pzl / t plz propagation delay a n to a=b 80 29 23 245 49 42 305 61 52 370 74 63 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.11; table 2 t pzl / t plz propagation delay b n to a=b 88 32 26 270 54 46 340 68 58 405 81 69 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.11; table 2 t phl / t plh propagation delay a n to f n 83 30 24 255 51 43 320 64 54 385 77 65 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b n to f n 85 31 25 265 53 45 330 66 56 400 80 68 ns 2.0 4.5 6.0 sum m=s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay a n to f n 77 28 22 240 48 41 300 60 51 360 72 61 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b n to f n 88 32 26 275 55 47 345 69 59 415 83 71 ns 2.0 4.5 6.0 diff m=s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 note ; figs 7 and 11 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) mode other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max.
1998 jun 10 11 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi voltages are referenced to gnd (ground = 0 v) note to the dc characteristics 1. the maximum operating output voltage (v o(max) ) is 6.0 v. note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v il other +25 - 40 to +85 - 40 to +125 min . typ. max. min . max. min. max. i oz high level output leakage current 0.5 5.0 10.0 m a 2.0 to 6.0 v il note 1 v o = 0 or 6 v input unit load coefficient c n , m 0.50 a n , b n 0.75 s n 1.00
1998 jun 10 12 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) mode other +25 - 40 to +85 - 40 to +125 min. typ. max . min. max. min. max. t phl / t plh propagation delay c n to c n+4 25 42 53 63 ns 4.5 sum diff m=0v; fig.9; tables 1 and 2 t phl / t plh propagation delay c n to f n 28 48 60 72 ns 4.5 sum diff m=0v; fig.9; tables 1 and 2 t phl / t plh propagation delay a n to g 31 54 68 81 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b n to g 32 54 68 81 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay a n to g 31 54 68 81 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b n to g 31 54 68 81 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay a n to p 23 41 51 62 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b n to p 24 41 51 62 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay a n to p 23 40 50 60 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b n to p 23 40 50 60 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay a i to f i 33 58 73 87 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b i to f i 34 58 73 87 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1
1998 jun 10 13 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 t phl / t plh propagation delay a i to f i 33 57 71 86 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay b i to f i 33 57 71 86 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay a i to f i 29 54 68 81 ns 4.5 logic m = 4.5 v; fig.8; table 3 t phl / t plh propagation delay b i to f i 33 54 68 81 ns 4.5 logic m = 4.5 v; fig.8; table 3 t phl / t plh propagation delay a n to c n+4 30 53 66 80 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.8; table 1 t phl / t plh propagation delay b n to c n+4 31 53 66 80 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.8; table 1 t phl / t plh propagation delay a n to c n+4 30 55 69 83 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.10; table 2 t phl / t plh propagation delay b n to c n+4 34 55 69 83 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.10; table 2 t pzl / t plz propagation delay a n to a=b 34 60 75 90 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.11; table 2 t pzl / t plz propagation delay b n to a=b 35 60 75 90 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.11; table 2 t phl / t plh propagation delay a n to f n 33 56 70 84 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 t phl / t plh propagation delay b n to f n 33 56 70 84 ns 4.5 sum m = s 1 =s 2 =0v; s 0 =s 3 = 4.5 v; fig.7; table 1 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) mode other +25 - 40 to +85 - 40 to +125 min. typ. max . min. max. min. max.
1998 jun 10 14 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 note to the ac characteristics 1. for the open drain output (a=b) only t thl is valid. t phl / t plh propagation delay a n to f n 32 56 70 84 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t phl / t plh propagation delay a n to f n 33 56 70 84 ns 4.5 diff m = s 0 =s 3 =0v; s 1 =s 2 = 4.5 v; fig.8; table 2 t thl / t tlh output transition time 7 15 19 22 ns 4.5 figs 7 and 11; note 1 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) mode other +25 - 40 to +85 - 40 to +125 min. typ. max . min. max. min. max.
1998 jun 10 15 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 ac waveforms fig.7 propagation delays for carry input to carry output, carry input to function outputs, operands to carry generate operands, propagation outputs and output transition lines. fig.8 propagation delays for operands to carry generate, propagate outputs and function outputs. fig.9 propagation delays for operands to carry output and function outputs. fig.10 propagation delays for operands to carry output. fig.11 waveforms showing the input (a i , b j ) to output (a=b) propagation delays and output transition time of the open drain output (a=b). note to ac waveforms application information (1) hc: v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.12 application example showing 16-bit alu ripple-carry configuration. a and b inputs and f outputs of 181 are not shown
1998 jun 10 16 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (millimetre dimensions are derived from the original inch dimensions) sot222-1 95-03-11 a min. a max. b z max. w m e e 1 1.63 1.14 0.56 0.43 0.36 0.25 31.9 31.5 6.73 6.48 3.51 3.05 0.25 2.54 7.62 8.13 7.62 10.03 7.62 2.05 4.70 0.38 3.94 0.064 0.045 0.022 0.017 0.014 0.010 1.256 1.240 0.265 0.255 0.138 0.120 0.01 0.100 0.300 0.32 0.30 0.395 0.300 0.081 0.185 0.015 0.155 ms-001af m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. pin 1 index (1) (1) (1) dip24: plastic dual in-line package; 24 leads (300 mil) sot222-1
1998 jun 10 17 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot101-1 92-11-17 95-01-23 a min. a max. b w m e e 1 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 3.9 3.4 0.25 2.54 15.24 15.80 15.24 17.15 15.90 2.2 5.1 0.51 4.0 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.15 0.13 0.01 0.10 0.60 0.62 0.60 0.68 0.63 0.087 0.20 0.020 0.16 051g02 mo-015ad m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. z max. (1) (1) (1) dip24: plastic dual in-line package; 24 leads (600 mil) sot101-1
1998 jun 10 18 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013ad pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 95-01-24 97-05-22
1998 jun 10 19 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 jun 10 20 philips semiconductors product speci?cation 4-bit arithmetic logic unit 74hc/hct181 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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